1. Field of the Invention
This disclosure relates to semiconductor devices, and more particularly, to a non-volatile memory such as an EEPROM (Electrically Erasable and Programmable Read Only Memory) and method of manufacturing the same.
2. Description of the Related Art
FIG. 1 is a sectional diagram illustrating the structure of a conventional EEPROM unit cell, which has been introduced to overcome the problems such as disturbance between adjacent memory cells, which can result in unintended program or erase operations of the adjacent memory cells.
Referring to FIG. 1, the conventional EEPROM unit cell consists of a memory transistor 20 and a select transistor 30 disposed on a substrate 10. The substrate 10 includes a common source region 50 and a drain region 60. The source region 50 includes a double diffusion structure including an n+ type high concentration impurity region 32 and an n− type low concentration impurity region 36. Likewise, the drain region 60 includes a double diffusion structure including an n+ type high concentration impurity region 33 and an n− type low concentration impurity region 37. The length L1, or the distance between the source region 50 and the drain region 60, is the width of the conventional EEPROM unit cell.
The substrate 10 also includes a channel region 40 that consists of an n− type low concentration impurity region 35. An n+ type high concentration impurity region 31 is disposed adjacent to the channel region 40, beneath the memory transistor 20.
The memory transistor 20 consists of a tunneling dielectric 15, a gate dielectric 17, a floating gate 21, an intergate insulating layer 22, a sense line 23, and spacers 18 disposed on the sidewalls of the floating gate 21, the intergate insulating layer 22, and the sense line 23.
The select transistor 30 consists of a word line 25 insulated from the substrate 10 by a gate dielectric 17. In addition, spacers 18 are disposed on the sidewalls of the word line 25. The length L2 is the distance between the sense line 23 and the word line 25. The conventional EEPROM unit cell overcomes the disturbance problem using the word line 25 which prevents the unintended program or erase operations of the nearby cells. Thus, with the conventional EEPROM unit cell, the sense line 23 and the word line 25 are required to be formed together.
Table 1 below illustrates the voltages that are applied to the conventional EEPROM unit cell during a charge, discharge, and read operation.
TABLE 1OperationSense LineWordSourceDrain regionSubstrateStatus23Line 25region 506010Charge 15 V17 VFloating  0 V0 V(erase)Discharge  0 V17 VFloating 15 V0 V(program)Read1.8 V1.8 V 0 V0.5 V0 V
During a charge or erase operation, a voltage of 15 V is applied to the sense line 23 and a voltage of 17 V is applied to the word line 25. The source region 50 is kept in a floating state while both the drain region 60 and substrate 10 are at a potential of 0 V. Fowler-Nordheim (F-N) tunneling occurs from the channel region 40 to the floating gate 21, having the effect of increasing the threshold voltage Vth of the device.
During a discharge or program operation of the device, a voltage of 0 V is applied to the sense line 23 and a voltage of 17 V is applied to the word line 25. The source region 50 is kept in a floating state while the drain region 60 has a voltage of 15 V applied to it, and the substrate 10 is held at 0 V. F-N tunneling occurs from the floating gate 21 to the channel region 40, having the effect of decreasing the threshold voltage Vth of the device.
During a read operation of the device, the “1” or “0” status of the device is read by sensing the charged or discharged status of the device. Both the sense line 23 and the word line 25 are maintained at a read voltage of about 1.8 V, while the drain region 60 is maintained at about 0.5 V. The source region 50 and the substrate 10 are at about 0V.
Disadvantages of the conventional EEPROM unit cell described above include that it has a relatively slow speed due to the F-N tunneling processes that occur during both the charge and discharge operations. Furthermore, both the sense line 23 and the word line 25 must be physically separated by a sufficient amount, thus the conventional EEPROM unit cell has a relatively large size, e.g., L1. Furthermore, it is difficult to reduce L1 because sufficient overlap margins between the impurity region 31 and the floating gate 21 need to be secured. As a result, additional reduction of the device sizes has become more difficult.
In addition, as the semiconductor devices have become more highly-integrated, the prior art problems such as punchthrough or program disturbance between the memory cells have become more serious. This is particularly true as the high voltages need to be applied to the junction regions for an F-N tunneling of electrons through the tunneling dielectric layer 15 during the program operation or the erase operation.
Embodiments of the invention address these and other disadvantages of the conventional art.